Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins

Ming-Dou Ker*, Chung-Yu Wu, Tao Cheng, Michael J.N. Wu, T. L. Yu, Alex C. Wang

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

6 Scopus citations

Abstract

An anomalous phenomenon of ESD failure in CMOS ICs with multiple VDD and VSS power-supply pins is discovered and investigated. A method of whole-chip ESD protection to overcome this anomalous ESD failure is proposed with experimental verification.

Original languageEnglish
Pages124-128
Number of pages5
StatePublished - 1 Dec 1994
EventProceedings of the 1994 International Integrated Reliability Workshop Final Report - Lake Tahoe, CA, USA
Duration: 16 Oct 199419 Oct 1994

Conference

ConferenceProceedings of the 1994 International Integrated Reliability Workshop Final Report
CityLake Tahoe, CA, USA
Period16/10/9419/10/94

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