A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the 1C during the ESD-stress condition, but this ESD clamp circuit is kept off when the 1C is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-im CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-im CMOS 1C product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.
- Esd clamp circuit