Whole-chip ESD protection design for submicron CMOS VLSI

Ming-Dou Ker*, Shue Chang Liu

*Corresponding author for this work

Research output: Contribution to journalConference article

7 Scopus citations

Abstract

A VDD-to-VSS ESD clamp circuit is designed to provide the real whole-chip ESD protection for submicron CMOS IC's. The ESD-protection efficiency is experimentally verified to be dependent on the pin location of a chip. This whole-chip ESD protection design has been successfully implemented in a 0.8-μm CMOS IC product with a real pin-to-pin ESD protection of above 3 KV.

Original languageEnglish
Pages (from-to)1920-1923
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
StatePublished - 1 Jan 1997
EventProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong
Duration: 9 Jun 199712 Jun 1997

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