Well-structured modified booth multiplier and its application to reconfigurable MAC design

Li Rong Wang*, Ming Hsien Tu, Shyh-Jye Jou, Chung Len Lee

*Corresponding author for this work

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 32 × 32, two 16 × 16 or four 8 × 8 signed multiply-accumulation. Experimentally, when implemented with a 130 nm CMOS single-Vt standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-Vt standard cell library.

Original languageEnglish
Pages (from-to)1112-1119
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE94-C
Issue number6
DOIs
StatePublished - 1 Jan 2011

Keywords

  • Mixed-Vt
  • Modified Booth encoding
  • Multiplier
  • Multiply-accumulator
  • Reconfigurable
  • Standard cell library

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