Well-behaved 4H-SiC PMOSFET with LOCal oxidation of SiC (LOCOSiC) isolation structure and compromised gate oxide for Sub-10V SiC CMOS application

Chia Lung Hung*, Bing Yue Tsui

*Corresponding author for this work

Research output: Contribution to journalReview articlepeer-review

2 Scopus citations

Abstract

SiC devices are suitable for high temperature applications due to its’ wide energy bandgap and high thermal conductivity. Some SiC CMOSFET ICs have been reported recently. However, less literature address the characteristics of SiC PMOSFET. In this work, we fabricated PMOSFET with Local Oxidation of SiC (LOCOSiC) isolation structure and different gate oxidation processes targeting sub-10V operation. Well behaved PMOSFET with suitable threshold voltage (−5.58 V), low subthreshold swing (200 mV/decade), acceptable hole mobility (3 cm2/V-sec), and low off-state current (<1 × 10−12 A/μm at −10 V) is achieved. Temperature dependence of device characteristics are investigated. These results make the implementation of high-performance CMOS a great progress.

Original languageEnglish
Article number107774
JournalSolid-State Electronics
Volume166
DOIs
StatePublished - Apr 2020

Keywords

  • Gate oxide
  • Isolation
  • Metal-oxide-semiconductor field effect transistor
  • Silicon carbide

Fingerprint Dive into the research topics of 'Well-behaved 4H-SiC PMOSFET with LOCal oxidation of SiC (LOCOSiC) isolation structure and compromised gate oxide for Sub-10V SiC CMOS application'. Together they form a unique fingerprint.

Cite this