Wafer-level bonding/stacking technology for 3D integration

Cheng Ta Ko, Kuan-Neng Chen*

*Corresponding author for this work

Research output: Contribution to journalArticle

123 Scopus citations

Abstract

Enhanced transmission speeds, lower power consumption, better performance, and smaller form factors are reported as advantages in many devices and applications when using 3D integration. One core technique for performing 3D interconnection is stacked bonding. In this paper, wafer-level bonding technologies are reviewed and described in detail, including bonding materials and bonding conditions. The corresponding 3D integration technologies and platforms developed world-wide are also organized and addressed.

Original languageEnglish
Pages (from-to)481-488
Number of pages8
JournalMicroelectronics Reliability
Volume50
Issue number4
DOIs
StatePublished - 1 Apr 2010

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