Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies

C. T. Ko*, Z. C. Hsiao, Y. J. Chang, P. S. Chen, J. H. Huang, H. C. Fu, Y. J. Huang, C. W. Chiang, W. L. Tsat, Y. H. Chen, W. C. Lo, Kuan-Neng Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

Cu TSV combination with Cu/Sn micro-joint to form vertical interconnection is a good alternative for 3D integration. The insertion loss of two chip stack was evaluated by simulation to realize the signal transmission effects in high speed digital signaling via TSV and micro-joint interconnect. To satisfy the throughput and cost requirement for mass production in future, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding was demonstrated. Key techniques including TSV fabrication, micro-bumping, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. This paper presents a complete study of structure design, process condition, electrical and reliability assessment of the wafer-level 3D integration scheme. The 3D integration scheme was assessed to be with excellent electrical performance and reliability, and is potentially to be applied for 3D IC applications.

Original languageEnglish
Title of host publication2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOIs
StatePublished - 1 Dec 2011
Event2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan
Duration: 31 Jan 20122 Feb 2012

Publication series

Name2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Conference

Conference2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
CountryJapan
CityOsaka
Period31/01/122/02/12

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