In this paper, a VLSI implementation of timing recovery (TR) and carrier recovery (CR) used in dual mode (QAM and VSB) transceiver for digital CATV will be introduced. The proposed TR uses a simple and baud-rate algorithm and the CR uses decision-directed approach with steep gradient algorithm, which can be used in both QAM and VSB signal. Thus, the hardware complexity for dual mode is dramatically reduced, while the performance is almost the same. Finally, the TR and CR are implemented by TSMC 0.6um 1P3M process. The total gate is 12985 and the core size is 2175 by 1237 um 2 . It consumes only 7.32 mW when operates at 2 V.
|Number of pages||4|
|Journal||International Symposium on VLSI Technology, Systems, and Applications, Proceedings|
|State||Published - 1 Jan 1999|
|Event||Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan|
Duration: 7 Jun 1999 → 10 Jun 1999