VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode

Shyh-Jye Jou*, Chun Hung Kuo, Muh Tian Shiau, Jung Yu Heh, Chrong Kuang Wang

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

5 Scopus citations

Abstract

In this paper, a VLSI implementation of timing recovery (TR) and carrier recovery (CR) used in dual mode (QAM and VSB) transceiver for digital CATV will be introduced. The proposed TR uses a simple and baud-rate algorithm and the CR uses decision-directed approach with steep gradient algorithm, which can be used in both QAM and VSB signal. Thus, the hardware complexity for dual mode is dramatically reduced, while the performance is almost the same. Finally, the TR and CR are implemented by TSMC 0.6um 1P3M process. The total gate is 12985 and the core size is 2175 by 1237 um 2 . It consumes only 7.32 mW when operates at 2 V.

Original languageEnglish
Pages (from-to)159-162
Number of pages4
JournalInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
DOIs
StatePublished - 1 Jan 1999
EventProceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan
Duration: 7 Jun 199910 Jun 1999

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