VLSI implementation of a low complexity 4×4 MIMO sphere decoder with table enumeration

Kai Jiun Yang, Shang-Ho Tsai, Ruei Ching Chang, Yan Cheng Chen, Gene C.H. Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

In this work a sphere decoder with low complexity is proposed and implemented. We propose a simplified norm algorithm, which is called admissible set elimination (ASE), to dramatically decrease the number of searching nodes. In addition, the decoder uses table-look-up to acquire the enumeration order of different constellations. As a result, the critical path is shortened and the throughput is enhanced. Compared to the optimal ML detector, the proposed scheme greatly improves the complexity and throughput, while the performance only degrades around 0.5 dB. The proposed scheme is fabricated by a TSMC 90 nm process. The area is 0.85 mm2, and the average throughput can be up to 411.3 Mbps when the clock rate is 108.7 MHz.

Original languageEnglish
Title of host publication2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages2167-2170
Number of pages4
DOIs
StatePublished - 9 Sep 2013
Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
Duration: 19 May 201323 May 2013

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
CountryChina
CityBeijing
Period19/05/1323/05/13

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  • Cite this

    Yang, K. J., Tsai, S-H., Chang, R. C., Chen, Y. C., & Chuang, G. C. H. (2013). VLSI implementation of a low complexity 4×4 MIMO sphere decoder with table enumeration. In 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 (pp. 2167-2170). [6572304] (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2013.6572304