VLSI implementation for MAC-level DWT architecture

Shiuh Rong Huang, Lan-Rong Dung

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


This paper presents a VLSI design methodology for the MAC-level DWT processor based on a novel limited-resource scheduling (LRS) algorithm. The r-split Fully-specified Signal Flow Graph (FSFG) of the limited-resource FIR filter has been developed for the scheduling of MAC-level DWT signal processing. Given a set of architecture constraints and DWT parameters, the LRS algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation, and the performance has also been investigated. Because the registers of FIR filtering are reused for the inter-octave storage, the MAC-level DWT architecture may require less extra inter-octave memory than the traditional architecture.

Original languageEnglish
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationNew Paradigms for VLSI Systems Design, ISVLSI 2002
EditorsAsim Smailagic, Robert Brodersen
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)0769514863
StatePublished - 1 Jan 2002
EventIEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002 - Pittsburgh, United States
Duration: 25 Apr 200226 Apr 2002

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477


ConferenceIEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002
CountryUnited States


  • Computer architecture
  • Design methodology
  • Discrete wavelet transforms
  • Finite impulse response filter
  • Flow graphs
  • Processor scheduling
  • Registers
  • Scheduling algorithm
  • Signal processing algorithms
  • Very large scale integration

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