VLSI focal-plane array processor for morphological image processing

W. C. Fang, T. Shaw, J. Yu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

A full-custom mixed-signal VLSI design for high-speed morphological image processing is developed by combining a two-dimensional fine-grain parallel array architecture with on-chip focal-plane photodetectors and transmitters. An 8∗8 array processor prototype chip is designed in a 1.2-mm∗1.2-mm silicon area using the MOSIS 2- mu m CMOS process.

Original languageEnglish
Title of host publicationProceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
PublisherIEEE Computer Society
Pages423-426
Number of pages4
ISBN (Electronic)0780307682
DOIs
StatePublished - 1 Jan 1992
Event5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 - Rochester, United States
Duration: 21 Sep 199225 Sep 1992

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Conference

Conference5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
CountryUnited States
CityRochester
Period21/09/9225/09/92

Fingerprint Dive into the research topics of 'VLSI focal-plane array processor for morphological image processing'. Together they form a unique fingerprint.

  • Cite this

    Fang, W. C., Shaw, T., & Yu, J. (1992). VLSI focal-plane array processor for morphological image processing. In Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 (pp. 423-426). [270255] (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASIC.1992.270255