VLSI design of the shuffle-exchange network for 2D fast transforms

Kuei-Ann Wen*, Po Wen Cheng, Ru Yeong Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A pipelined shuffle-exchange network is proposed as a generalized 2D orthogonal transforms with flexible transform lengths. The 16×16 points 2-D DCT processor is chosen as the target design for its applicability in video processing. It is constructed in a modulized radix-4 pipelined structure and is implemented with high data rate and low hardware cost. According to the circuit simulations with 1.2 μm standard cell technology, the processing throughput of this DCT circuit can be 40 MHz. Extensibility for various indices and transform lengths is also discussed. Besides, a number of orthogonal transform algorithms are also implemented in the shuffle-exchange network with the same throughput rate.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages754-757
Number of pages4
ISBN (Print)0780312813
DOIs
StatePublished - 1 Jan 1993
Event1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA
Duration: 3 May 19936 May 1993

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume1
ISSN (Print)0271-4310

Conference

Conference1993 IEEE International Symposium on Circuits and Systems
CityChicago, IL, USA
Period3/05/936/05/93

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    Wen, K-A., Cheng, P. W., & Lin, R. Y. (1993). VLSI design of the shuffle-exchange network for 2D fast transforms. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 754-757). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 1). Publ by IEEE. https://doi.org/10.1109/ISCAS.1993.393831