VLSI design of a cellular-automata based logic and fault emulator

Yih-Lang Li*, Ying Chao Lai, Cheng Wen Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

With advances in VLSI technology and the decline in hardware costs, special-purpose machines have become more and more popular for a wide range of applications. We have proposed a unilateral 2-D cellular automata (CA) model which can be treated as an SIMD parallel architecture. In this paper, we present a CA chip which realizes our previously proposed CA model for highly parallel logic and fault simulation. By using pipelining, our CA simulation engine achieves a simulation rate of more than one billion gate evaluations per second using a 20 MHz clock and 8-bit words. The CA architecture allows easy scaling; i.e., each CA chip can directly communicate with its four neighboring CA chips to construct a larger cellular array. Our CA chip operates in either initialization or simulation mode and can perform logic and fault simulation. It produces one output in every six clock cycles after the pipeline has been filled. Compared with previously reported parallel fault simulators, its performance is superior by about three orders of magnitude.

Original languageEnglish
Pages (from-to)189-199
Number of pages11
JournalProceedings of the National Science Council, Republic of China, Part A: Physical Science and Engineering
Volume21
Issue number3
StatePublished - 1 May 1997

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