VLSI architecture for real-time HD1080p view synthesis engine

Ying Rung Horng*, Yu Cheng Tseng, Tian-Sheuan Chang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

27 Scopus citations

Abstract

This paper presents a real-time HD1080p view synthesis engine based on the reference algorithm from 3-D video coding team by solving high computational complexity and high memory cost problems. For the computational complexity, we propose the bilinear interpolation to simplify the hole filling process, and the Z scaling method with floating-point format to reduce the cost of homography calculation. For the memory cost, we propose the frame-level pipelining to reduce the requirement of warped depth maps, and the column-order warping method to remove the Z-buffer in occlusion handling. With the 90 nm complementary metal-oxide-semiconductor technology, our view synthesis engine can archive the throughput of 32.4 f/s for HD1080p videos with the gate count of 268.5 K and the internal memory of 69.4 kbytes. The experimental result shows our implementation has the similar synthesis quality as the original reference algorithm.

Original languageEnglish
Article number5759074
Pages (from-to)1329-1340
Number of pages12
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume21
Issue number9
DOIs
StatePublished - 1 Sep 2011

Keywords

  • 3-D video coding
  • VLSI design
  • view synthesis

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