VLSI architecture design of motion estimator and in-loop filter for MPEG-4 AVC/H.264 encoders

Yiteh Yi Wang*, Yan Tsung Peng, Chun-Jen Tsai

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

7 Scopus citations

Abstract

In this paper, a new complexity-reduced method and its hardware architecture for motion estimation and the in-loop filter for MPEG-4 AVC/H.264 is proposed. The feature of the proposed method is focused on the computation reduction for the motion search algorithm among multiple reference frames and the mode partition determination. Furthermore, to verify the functionality and performance of the proposed hardware design, an emulation board platform, the ARM Integrator, is used for H.264 hardware/software co-development. The experimental results show that the proposed method has excellent performance with little or no degradation of coding efficiency.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
DOIs
StatePublished - 7 Sep 2004
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: 23 May 200426 May 2004

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