Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique

Meng Fan Chang*, Ding Ming Kwai, Kuei-Ann Wen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Crosstalk between bit lines leads to read-1 failure in a high-speed via-programmable read only memory (ROM) and limits the coverage of applicable code patterns. Due to the fluctuations in bit-line intrinsic and coupling capacitances, the amount of noise coupled to a selected bit line may vary, resulting in the reduction of sensing margin. In this paper, we propose a dynamic bit-line shielding (DBS) technique, suitable to be implemented in compilable ROM, to eliminate the crosstalk-induced read failure and to achieve full code coverage. Experiments of the 256Kb instances with and without the DBS circuit were undertaken using 0.25μm and 0.18 μm standard CMOS processes. The test results demonstrate the read-1 failures and confirm that the DBS technique can remove them successfully, allowing the ROM to operate under a wide range of supply voltage.

Original languageEnglish
Title of host publicationProceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005
Pages16-21
Number of pages6
DOIs
StatePublished - 9 Dec 2005
EventProceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005 - Taipei, Taiwan
Duration: 3 Aug 20055 Aug 2005

Publication series

NameRecords of the IEEE International Workshop on Memory Technology, Design and Testing
ISSN (Print)1087-4852

Conference

ConferenceProceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005
CountryTaiwan
CityTaipei
Period3/08/055/08/05

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  • Cite this

    Chang, M. F., Kwai, D. M., & Wen, K-A. (2005). Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique. In Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005 (pp. 16-21). (Records of the IEEE International Workshop on Memory Technology, Design and Testing). https://doi.org/10.1109/MTDT.2005.36