Abstract
We report very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good φm-eff of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85°C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
| Original language | English |
|---|---|
| Article number | 4418939 |
| Pages (from-to) | 333-336 |
| Number of pages | 4 |
| Journal | Technical Digest - International Electron Devices Meeting, IEDM |
| DOIs | |
| State | Published - 1 Dec 2007 |
| Event | 2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States Duration: 10 Dec 2007 → 12 Dec 2007 |
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Cheng, C. F., Wu, C. H., Su, N. C., Wang, S. J., McAlister, S. P., & Chin, A. (2007). Very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions. Technical Digest - International Electron Devices Meeting, IEDM, 333-336. [4418939]. https://doi.org/10.1109/IEDM.2007.4418939