Very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions

C. F. Cheng, C. H. Wu, N. C. Su, S. J. Wang, S. P. McAlister, Albert Chin

Research output: Contribution to journalConference article

29 Scopus citations

Abstract

We report very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good φm-eff of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85°C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.

Original languageEnglish
Article number4418939
Pages (from-to)333-336
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
DOIs
StatePublished - 1 Dec 2007
Event2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States
Duration: 10 Dec 200712 Dec 2007

Fingerprint Dive into the research topics of 'Very low V<sub>t</sub> [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions'. Together they form a unique fingerprint.

  • Cite this