Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

Chris Chun Chih Chung, Chiuan Huei Shen, Jer Yi Lin, Chun Chieh Chin, Tien-Sheng Chao*

*Corresponding author for this work

Research output: Contribution to journalArticle

12 Scopus citations

Abstract

We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal budget and 2) adopting high- {k} metal gate low-temperature process and realizing gate-all-around structure, which shows better subthreshold characteristics. Feasibility of improving current level within the same footprint and without degrading subthreshold performance is demonstrated. Series resistance limit is pointed out as a bottle neck for current increment with respect to layers of channels. Further investigation of reducing the series resistance of VSC nanowire is needed for any future circuit integration.

Original languageEnglish
Article number8233410
Pages (from-to)756-762
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume65
Issue number2
DOIs
StatePublished - 1 Feb 2018

Keywords

  • Cantilever
  • high-k metal gate (HKMG)
  • junctionless
  • nanowire
  • series resistance
  • vertically stacked.

Fingerprint Dive into the research topics of 'Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit'. Together they form a unique fingerprint.

  • Cite this