Vertically-stacked bottom- and top- gate polycrystalline silicon TFTs for three dimensional integrated circuit

I. Che Lee*, Tsung Che Tsai, Chun Chien Tsai, Po Yu Yang, Chao Lung Wang, Huang-Chung Cheng

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A high-performance poly-Si TFT with bottom-gate structure and a top-gate poly-Si TFT were vertically stacked for three dimensional integrated circuit. Consequently, the n-channel poly-Si TFTs with bottom-gate structure on the bottom layer showed considerably improved electrical characteristics, such as a high field effect mobility of 390 cm2/V-s due to the large lateral grain formed in the channel. The vertically stacked p-channel poly-Si TFTs with top-gate structure on the top layer showed a high field effect mobility of 131 cm2/V-s. Therefore, the proposed structure is very suitable for future 3D-IC and nano-device application.

Original languageEnglish
Title of host publication4th IEEE International NanoElectronics Conference, INEC 2011
DOIs
StatePublished - 26 Sep 2011
Event4th IEEE International Nanoelectronics Conference, INEC 2011 - Tao-Yuan, Taiwan
Duration: 21 Jun 201124 Jun 2011

Publication series

NameProceedings - International NanoElectronics Conference, INEC
ISSN (Print)2159-3523

Conference

Conference4th IEEE International Nanoelectronics Conference, INEC 2011
CountryTaiwan
CityTao-Yuan
Period21/06/1124/06/11

Keywords

  • 3D-IC
  • bottom gate
  • Poly-Si
  • TFTs
  • top gate

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    Lee, I. C., Tsai, T. C., Tsai, C. C., Yang, P. Y., Wang, C. L., & Cheng, H-C. (2011). Vertically-stacked bottom- and top- gate polycrystalline silicon TFTs for three dimensional integrated circuit. In 4th IEEE International NanoElectronics Conference, INEC 2011 [5991740] (Proceedings - International NanoElectronics Conference, INEC). https://doi.org/10.1109/INEC.2011.5991740