Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

Chun Yu Lin, Pin Hsin Chang, Rong Kun Chang, Ming-Dou Ker, Wen Tai Wang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.

Original languageEnglish
Title of host publicationProceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages255-258
Number of pages4
ISBN (Electronic)9781479999286, 9781479999286
DOIs
StatePublished - 25 Aug 2015
Event22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 - Hsinchu, Taiwan
Duration: 29 Jun 20152 Jul 2015

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume2015-August

Conference

Conference22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
CountryTaiwan
CityHsinchu
Period29/06/152/07/15

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