Verification on port connections

Geeng Wei Lee*, Chun Yao Wang, Juinn-Dar Huang, Jing Yang Jou

*Corresponding author for this work

Research output: Contribution to journalConference article

Abstract

In a system-on-a-chip (SOC) design, several to hundreds of design blocks or intellectual properties (IPs) are integrated to form a complex function. Prior to verify the functionality of the integrated IPs, it is very important to ensure the correctness of the port connections among these IPs. This paper addresses the problem of verification on port connections while IPs are integrated into a larger block or a system, and presents a new connection model and the corresponding error model for port connections. An algorithm providing the minimum pattern set and a general verification flow used to verify port connections are also proposed.

Original languageEnglish
Pages (from-to)830-836
Number of pages7
JournalProceedings - International Test Conference
DOIs
StatePublished - 1 Dec 2004
EventProceedings - International Test Conference 2004 - Charlotte, NC, United States
Duration: 26 Oct 200428 Oct 2004

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