In a system-on-a-chip (SOC) design, several to hundreds of design blocks or intellectual properties (IPs) are integrated to form a complex function. Prior to verify the functionality of the integrated IPs, it is very important to ensure the correctness of the port connections among these IPs. This paper addresses the problem of verification on port connections while IPs are integrated into a larger block or a system, and presents a new connection model and the corresponding error model for port connections. An algorithm providing the minimum pattern set and a general verification flow used to verify port connections are also proposed.
|Number of pages||7|
|Journal||Proceedings - International Test Conference|
|State||Published - 1 Dec 2004|
|Event||Proceedings - International Test Conference 2004 - Charlotte, NC, United States|
Duration: 26 Oct 2004 → 28 Oct 2004