Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM

Ming Fu Tsai*, Jen Huan Tsai, Ming Long Fan, Pin Su, Ching Te Chuang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

In this paper, we propose three Current-Latch-based Sense Amplifiers (CLSA) configurations for nanoscale Bulk-CMOS SRAM and several CLSAs using FinFET devices with independently-controlled-gate. Extensive simulations suggest the proposed structures are robust against random offset errors. The proposed CLSA structures feature significant offset suppression capabilities with σ offset reduction up to 74% (76%) in 40nm Bulk-CMOS (25nm FinFET-SOI) technology compared with the conventional CLSA. Meanwhile, up to 27% (52%) shorter sensing delay, 71% (77%) shorter Time-To-Sense and 73% (76%) lower bit-line power consumption are achieved in 40nm Bulk-CMOS (25nm FinFET-SOI). Finally, the proposed CLSA structures significantly enhance the sensing yield and affordable number of cells per bit-line, thus improving the array efficiency hence overall area and performance/power as well.

Original languageEnglish
Title of host publication2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Pages471-474
Number of pages4
DOIs
StatePublished - 1 Dec 2012
Event2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung, Taiwan
Duration: 2 Dec 20125 Dec 2012

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
CountryTaiwan
CityKaohsiung
Period2/12/125/12/12

Keywords

  • Current-Latch-Based Sense Amplifier
  • FinFET
  • Offset
  • SRAM
  • Yield

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