Parasitic capacitance is a critical challenge in improving the device and circuit performance in nanoscale devices like the UTBSOI MOSFET and FinFET. Scaling the contact pitch decreases the separation between the gate and the source/drain contacts which increases the contribution of parasitic capacitance to the total capacitance as the devices are scaled. According to ITRS 2.0, the parasitic capacitance should be limited to be less than 60% of the total capacitance . For sub- 20 nm node devices, introduction of source/drain underlaps improves the short-channel performance . The additional resistance due to underlaps can be reduced by the introduction of higher-K spacers [3,4], and dual-K spacers trading-off parasitic capacitance [5-7]. On the other end, since air or vacuum has a dielectric constant of 1, vacuum or air-gap spacers can reduce the parasitic capacitance [8-12]. In underlapped nanoscale devices, corner spacer design in which a higher-K oxide is present only in the bottom corner of the gate and the rest of the spacer consists of a lower-K dielectric will be required to simultaneously reduce underlap resistance and parasitic capacitance [13-15]. Fig. 1 shows the different spacer design options explored such as the full spacer, dual-K spacer and corner spacer. The full spacer has a single dielectric material. The dual-K spacer has an inner higher-K and an outer lower-K dielectric. The corner spacer has a higher-K dielectric present only at the bottom corner of the gate and the rest of the spacer region is made up of a lower-K dielectric. The impact of corner spacer design on UTBSOI MOSFET has not been studied. In this paper, using TCAD simulations, we design and optimize corner spacer for UTBSOI MOSFET for the 11/10 nm node.