Using power gating techniques in area-array SoC floorplan design

Chi Yi Yeh*, Hung-Ming Chen, Li Da Huang, Wei Ting Wei, Chao Hung Lu, Chien-Nan Liu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Low power demand drives the development of lower power design architectures, among which power gating is one of the state-of-the-art techniques to achieve low power. MTCMOS (or sleep transistor) is applied when some of the blocks can be switched off without leakage power dissipation. This technique is widely used in circuit level design, but hardly used in higher level design stage. Due to early planning in power delivery for area-array design style, it is necessary to consider the power gating techniques in early SoC physical design stage. This paper presents a framework to insert coarse grain MTCMOS in SoC floorplanning stage, saving mainly leakage power. This work decides which modules have chance to save power by sleep transistors insertion, and reserves enough area for them during floorplanning. The results show that our approach works well and can obtain lower power floorplans with supply noise aware sleep transistor insertion in area-array architecture.

Original languageEnglish
Title of host publicationProceedings - 20th Anniversary IEEE International SOC Conference
Pages233-236
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan
Duration: 26 Sep 200729 Sep 2007

Publication series

NameProceedings - 20th Anniversary IEEE International SOC Conference

Conference

Conference20th Anniversary IEEE International SOC Conference
CountryTaiwan
CityHsinchu
Period26/09/0729/09/07

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