User verify and disturb mechanisms in a 65nm flash FPGA

James Yingbo Jia*, Pavan Singaraju, Fethi Dhaoui, Rich Newell, Patty Liu, Habtom Micael, Michael Traas, Salim Sammie, J. J. Wang, Frank Hawley, John McCollum, Van Den Abeelen Werner, Esmat Hamdy, Chen-Ming Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We present a study of the disturb mechanism encountered in a novel user verify technique that can be used to enhance the security of a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. Two disturb mechanisms are studied in detail. The intrinsic disturb mode is related to Fowler-Nordheim (FN) tunneling, whereas an extrinsic disturb mode involves traps which enhance the tunneling probability. The effect of single and multiple positive charges is simulated. It is concluded that multiple charges are involved during disturb to explain the observed extrinsic behavior. Accelerated testing predicts that 10k verify operations can be performed with an error rate less than 1ppm for a five million gate FPGA, equivalent to a FIT rate of approx. 0.001 failures per 10 9 hours per million gates when applied over a 20 year lifetime. The low verify-induced error rate makes the technique suitable for enhancing security by providing timely detection of malicious tampering attacks.

Original languageEnglish
Title of host publication2011 IEEE International Integrated Reliability Workshop Final Report, IRW 2011
Pages47-49
Number of pages3
DOIs
StatePublished - 1 Dec 2011
Event2011 30th IEEE International Integrated Reliability Workshop Final Report, IRW 2011 - South Lake Tahoe, CA, United States
Duration: 16 Oct 201120 Oct 2011

Publication series

NameIEEE International Integrated Reliability Workshop Final Report

Conference

Conference2011 30th IEEE International Integrated Reliability Workshop Final Report, IRW 2011
CountryUnited States
CitySouth Lake Tahoe, CA
Period16/10/1120/10/11

Fingerprint Dive into the research topics of 'User verify and disturb mechanisms in a 65nm flash FPGA'. Together they form a unique fingerprint.

  • Cite this

    Jia, J. Y., Singaraju, P., Dhaoui, F., Newell, R., Liu, P., Micael, H., Traas, M., Sammie, S., Wang, J. J., Hawley, F., McCollum, J., Den Abeelen Werner, V., Hamdy, E., & Hu, C-M. (2011). User verify and disturb mechanisms in a 65nm flash FPGA. In 2011 IEEE International Integrated Reliability Workshop Final Report, IRW 2011 (pp. 47-49). [6142586] (IEEE International Integrated Reliability Workshop Final Report). https://doi.org/10.1109/IIRW.2011.6142586