User verify and disturb mechanisms in a 65nm flash FPGA

James Yingbo Jia; Pavan Singaraju; Fethi Dhaoui; Rich Newell; Patty Liu; Habtom Micael; Michael Traas; Salim Sammie; J. J. Wang; Frank Hawley; John McCollum; Van Den Abeelen Werner; Esmat Hamdy; Chen-Ming Hu

doi:10.1109/IIRW.2011.6142586

User verify and disturb mechanisms in a 65nm flash FPGA

James Yingbo Jia^*, Pavan Singaraju, Fethi Dhaoui, Rich Newell, Patty Liu, Habtom Micael, Michael Traas, Salim Sammie, J. J. Wang, Frank Hawley, John McCollum, Van Den Abeelen Werner, Esmat Hamdy, Chen-Ming Hu

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

We present a study of the disturb mechanism encountered in a novel user verify technique that can be used to enhance the security of a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. Two disturb mechanisms are studied in detail. The intrinsic disturb mode is related to Fowler-Nordheim (FN) tunneling, whereas an extrinsic disturb mode involves traps which enhance the tunneling probability. The effect of single and multiple positive charges is simulated. It is concluded that multiple charges are involved during disturb to explain the observed extrinsic behavior. Accelerated testing predicts that 10k verify operations can be performed with an error rate less than 1ppm for a five million gate FPGA, equivalent to a FIT rate of approx. 0.001 failures per 10 ⁹ hours per million gates when applied over a 20 year lifetime. The low verify-induced error rate makes the technique suitable for enhancing security by providing timely detection of malicious tampering attacks.

Original language	English
Title of host publication	2011 IEEE International Integrated Reliability Workshop Final Report, IRW 2011
Pages	47-49
Number of pages	3
DOIs	https://doi.org/10.1109/IIRW.2011.6142586
State	Published - 1 Dec 2011
Event	2011 30th IEEE International Integrated Reliability Workshop Final Report, IRW 2011 - South Lake Tahoe, CA, United States Duration: 16 Oct 2011 → 20 Oct 2011

Publication series

Name	IEEE International Integrated Reliability Workshop Final Report

Conference

Conference	2011 30th IEEE International Integrated Reliability Workshop Final Report, IRW 2011
Country	United States
City	South Lake Tahoe, CA
Period	16/10/11 → 20/10/11

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Jia, J. Y., Singaraju, P., Dhaoui, F., Newell, R., Liu, P., Micael, H., Traas, M., Sammie, S., Wang, J. J., Hawley, F., McCollum, J., Den Abeelen Werner, V., Hamdy, E., & Hu, C-M. (2011). User verify and disturb mechanisms in a 65nm flash FPGA. In 2011 IEEE International Integrated Reliability Workshop Final Report, IRW 2011 (pp. 47-49). [6142586] (IEEE International Integrated Reliability Workshop Final Report). https://doi.org/10.1109/IIRW.2011.6142586

Jia, James Yingbo ; Singaraju, Pavan ; Dhaoui, Fethi ; Newell, Rich ; Liu, Patty ; Micael, Habtom ; Traas, Michael ; Sammie, Salim ; Wang, J. J. ; Hawley, Frank ; McCollum, John ; Den Abeelen Werner, Van ; Hamdy, Esmat ; Hu, Chen-Ming. / User verify and disturb mechanisms in a 65nm flash FPGA. 2011 IEEE International Integrated Reliability Workshop Final Report, IRW 2011. 2011. pp. 47-49 (IEEE International Integrated Reliability Workshop Final Report).

@inproceedings{9a59b659a68043e2adb587fa14c47a13,

title = "User verify and disturb mechanisms in a 65nm flash FPGA",

abstract = "We present a study of the disturb mechanism encountered in a novel user verify technique that can be used to enhance the security of a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. Two disturb mechanisms are studied in detail. The intrinsic disturb mode is related to Fowler-Nordheim (FN) tunneling, whereas an extrinsic disturb mode involves traps which enhance the tunneling probability. The effect of single and multiple positive charges is simulated. It is concluded that multiple charges are involved during disturb to explain the observed extrinsic behavior. Accelerated testing predicts that 10k verify operations can be performed with an error rate less than 1ppm for a five million gate FPGA, equivalent to a FIT rate of approx. 0.001 failures per 10 9 hours per million gates when applied over a 20 year lifetime. The low verify-induced error rate makes the technique suitable for enhancing security by providing timely detection of malicious tampering attacks.",

author = "Jia, {James Yingbo} and Pavan Singaraju and Fethi Dhaoui and Rich Newell and Patty Liu and Habtom Micael and Michael Traas and Salim Sammie and Wang, {J. J.} and Frank Hawley and John McCollum and {Den Abeelen Werner}, Van and Esmat Hamdy and Chen-Ming Hu",

year = "2011",

month = dec,

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doi = "10.1109/IIRW.2011.6142586",

language = "English",

isbn = "9781457701153",

series = "IEEE International Integrated Reliability Workshop Final Report",

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Jia, JY, Singaraju, P, Dhaoui, F, Newell, R, Liu, P, Micael, H, Traas, M, Sammie, S, Wang, JJ, Hawley, F, McCollum, J, Den Abeelen Werner, V, Hamdy, E & Hu, C-M 2011, User verify and disturb mechanisms in a 65nm flash FPGA. in 2011 IEEE International Integrated Reliability Workshop Final Report, IRW 2011., 6142586, IEEE International Integrated Reliability Workshop Final Report, pp. 47-49, 2011 30th IEEE International Integrated Reliability Workshop Final Report, IRW 2011, South Lake Tahoe, CA, United States, 16/10/11. https://doi.org/10.1109/IIRW.2011.6142586

User verify and disturb mechanisms in a 65nm flash FPGA. / Jia, James Yingbo; Singaraju, Pavan; Dhaoui, Fethi; Newell, Rich; Liu, Patty; Micael, Habtom; Traas, Michael; Sammie, Salim; Wang, J. J.; Hawley, Frank; McCollum, John; Den Abeelen Werner, Van; Hamdy, Esmat; Hu, Chen-Ming.

2011 IEEE International Integrated Reliability Workshop Final Report, IRW 2011. 2011. p. 47-49 6142586 (IEEE International Integrated Reliability Workshop Final Report).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Singaraju, Pavan

AU - Dhaoui, Fethi

AU - Newell, Rich

AU - Liu, Patty

AU - Micael, Habtom

AU - Traas, Michael

AU - Sammie, Salim

AU - Wang, J. J.

AU - Hawley, Frank

AU - McCollum, John

AU - Den Abeelen Werner, Van

AU - Hamdy, Esmat

AU - Hu, Chen-Ming

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N2 - We present a study of the disturb mechanism encountered in a novel user verify technique that can be used to enhance the security of a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. Two disturb mechanisms are studied in detail. The intrinsic disturb mode is related to Fowler-Nordheim (FN) tunneling, whereas an extrinsic disturb mode involves traps which enhance the tunneling probability. The effect of single and multiple positive charges is simulated. It is concluded that multiple charges are involved during disturb to explain the observed extrinsic behavior. Accelerated testing predicts that 10k verify operations can be performed with an error rate less than 1ppm for a five million gate FPGA, equivalent to a FIT rate of approx. 0.001 failures per 10 9 hours per million gates when applied over a 20 year lifetime. The low verify-induced error rate makes the technique suitable for enhancing security by providing timely detection of malicious tampering attacks.

AB - We present a study of the disturb mechanism encountered in a novel user verify technique that can be used to enhance the security of a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. Two disturb mechanisms are studied in detail. The intrinsic disturb mode is related to Fowler-Nordheim (FN) tunneling, whereas an extrinsic disturb mode involves traps which enhance the tunneling probability. The effect of single and multiple positive charges is simulated. It is concluded that multiple charges are involved during disturb to explain the observed extrinsic behavior. Accelerated testing predicts that 10k verify operations can be performed with an error rate less than 1ppm for a five million gate FPGA, equivalent to a FIT rate of approx. 0.001 failures per 10 9 hours per million gates when applied over a 20 year lifetime. The low verify-induced error rate makes the technique suitable for enhancing security by providing timely detection of malicious tampering attacks.

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