@inproceedings{9a59b659a68043e2adb587fa14c47a13,
title = "User verify and disturb mechanisms in a 65nm flash FPGA",
abstract = "We present a study of the disturb mechanism encountered in a novel user verify technique that can be used to enhance the security of a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. Two disturb mechanisms are studied in detail. The intrinsic disturb mode is related to Fowler-Nordheim (FN) tunneling, whereas an extrinsic disturb mode involves traps which enhance the tunneling probability. The effect of single and multiple positive charges is simulated. It is concluded that multiple charges are involved during disturb to explain the observed extrinsic behavior. Accelerated testing predicts that 10k verify operations can be performed with an error rate less than 1ppm for a five million gate FPGA, equivalent to a FIT rate of approx. 0.001 failures per 10 9 hours per million gates when applied over a 20 year lifetime. The low verify-induced error rate makes the technique suitable for enhancing security by providing timely detection of malicious tampering attacks.",
author = "Jia, {James Yingbo} and Pavan Singaraju and Fethi Dhaoui and Rich Newell and Patty Liu and Habtom Micael and Michael Traas and Salim Sammie and Wang, {J. J.} and Frank Hawley and John McCollum and {Den Abeelen Werner}, Van and Esmat Hamdy and Chen-Ming Hu",
year = "2011",
month = dec,
day = "1",
doi = "10.1109/IIRW.2011.6142586",
language = "English",
isbn = "9781457701153",
series = "IEEE International Integrated Reliability Workshop Final Report",
pages = "47--49",
booktitle = "2011 IEEE International Integrated Reliability Workshop Final Report, IRW 2011",
note = "null ; Conference date: 16-10-2011 Through 20-10-2011",
}