Universal architectures for Reed-Solomon error-and-erasure decoder

Fu Ke Chang*, Chien Ching Lin, Hsie Chia Chang, Chen Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations


This paper presents the universal architecture for Reed Solomon (RS) error-and-erasure decoder that can accommodate any codeword with different code parameters and finite field definitions. In comparison with other reconfigurable RS decoders, the proposed design, based on the Montgomery multiplication algorithm, can support various finite field degrees, different primitive polynomials, and erasure decoding functions. In addition, the decoder features an on-the-fly finite field inversion table for high speed error evaluation. The area efficient design approach is also presented. Implemented with 1.2V 0.13μm 1P8M technology, this decoder, correcting up to 16 errors, can operate at 300MHz and reach a 2.4Gb/s data rate. The total gate count is about 54K and the core size is 0.36mm2. The average power consumption is 20.2mW.

Original languageEnglish
Title of host publication2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
PublisherIEEE Computer Society
Number of pages4
ISBN (Print)0780391624, 9780780391628
StatePublished - 1 Jan 2005
Event1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan
Duration: 1 Nov 20053 Nov 2005

Publication series

Name2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005


Conference1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Fingerprint Dive into the research topics of 'Universal architectures for Reed-Solomon error-and-erasure decoder'. Together they form a unique fingerprint.

Cite this