Unified cellular array for multiplication, division and square root

Sau-Gee Chen*, Chieh Chih Li

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

A unified fast, small-area processor capable of executing multiplication, division and square-root operations, all starting from MSD is proposed. Unlike the existing designs which require both addition and subtraction operations, and complicated estimator for DIV/SQRT result digits, the proposed design consists of only addition operations and no complicated estimator. By taking negative absolute values of partial remainders, the algorithm breaks the sequential tie between residue sign detection and the next remainder update operations. As such, these two operations can be parallely and independently performed. The proposed architecture has smaller area and more regular structure than the known designs.

Original languageEnglish
Pages533-541
Number of pages9
StatePublished - 1 Dec 1995
EventProceedings of the 1995 IEEE Workshop on VLSI Signal Processing - Osaka, Jpn
Duration: 16 Oct 199518 Oct 1995

Conference

ConferenceProceedings of the 1995 IEEE Workshop on VLSI Signal Processing
CityOsaka, Jpn
Period16/10/9518/10/95

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  • Cite this

    Chen, S-G., & Li, C. C. (1995). Unified cellular array for multiplication, division and square root. 533-541. Paper presented at Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing, Osaka, Jpn, .