A unified fast, small-area processor capable of executing multiplication, division and square-root operations, all starting from MSD is proposed. Unlike the existing designs which require both addition and subtraction operations, and complicated estimator for DIV/SQRT result digits, the proposed design consists of only addition operations and no complicated estimator. By taking negative absolute values of partial remainders, the algorithm breaks the sequential tie between residue sign detection and the next remainder update operations. As such, these two operations can be parallely and independently performed. The proposed architecture has smaller area and more regular structure than the known designs.
|Number of pages||9|
|State||Published - 1 Dec 1995|
|Event||Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing - Osaka, Jpn|
Duration: 16 Oct 1995 → 18 Oct 1995
|Conference||Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing|
|Period||16/10/95 → 18/10/95|