Unified bit-parallel arithmetic processor using redundant binary representation

Sau-Gee Chen*

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

An addition rule for signed-digit representation (SDR), generalized from the addition rule of redundant binary representation, is proposed which is free from carry-propagation. The MSD (most significant digit)-first multiplication operation is easily devised by incorporating hardware redundancy with the redundancy in this addition rule. By combing the all MSD-first arithmetic operations, a unified arithmetic processor is obtained which can perform division, multiplication, and square-root operations. This unified processor is similar in structure to an array multiplier. It provides three advantages over the conventional arithmetic unit: (1) higher speed, (2) more functional capability, and (3) better area utilization. It is also suitable for VLSI implementation.

Original languageEnglish
Pages91-96
Number of pages6
StatePublished - 1 Dec 1989
EventEighth Annual International Phoenix Conference on Computers and Communications - 1989 Conference Proceedings - Scottsdale, AZ, USA
Duration: 22 Mar 198924 Mar 1989

Conference

ConferenceEighth Annual International Phoenix Conference on Computers and Communications - 1989 Conference Proceedings
CityScottsdale, AZ, USA
Period22/03/8924/03/89

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