Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution

Ming-Dou Ker*, Cheng Cheng Yen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Four different on-chip power-rail electrostatic discharge (ESD) clamp circuits have been designed to investigate their susceptibility to electrical fast transient (EFT) test. From the experimental results, the feedback loop in two kinds of on-chip power-rail ESD clamp circuits provides the lock function to perform a latchup-like failure after the EFT test. The re-design solution will be developed to overcome this issue to meet the regulation of EFT/EMC test.

Original languageEnglish
Title of host publicationProceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC
Pages69-72
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event18th International Zurich Symposium on Electromagnetic Compatibility, EMC - Munich, Germany
Duration: 24 Sep 200728 Sep 2007

Publication series

NameProceedings of the 18th International Zurich Symposium on Electromagnetic Compatibility, EMC

Conference

Conference18th International Zurich Symposium on Electromagnetic Compatibility, EMC
CountryGermany
CityMunich
Period24/09/0728/09/07

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