Uneven-Topography-Chip Packing Approach Using Double-Self-Assembly Technology for 3-D Heterogeneous Integration

Wen Wei Shen, Hsiao Chun Chang, Yu Tao Yang, Yu Chen Hu, Kuan-Neng Chen*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


Although chip-level heterogeneous integration has high yield for production, low-throughput issue of chip-to-wafer bonding is necessary to be improved. Due to the uneven topography and small chip size, handling issue and alignment accuracy are important factors that impact the difficulty in heterogeneous integration. Self-assembly technology has a high potential to be applied in 3-D heterogeneous integration. By using hydrophobic film to define the stacking area, hydrophilic chips can be assembled to realize alignment process on these areas through wafer surface tension in a very short time. With this concept, double-self-assembly technology is accomplished to resolve both handling and alignment issues for uneven-topography-chip integration. In this paper, different chip sizes of μ-pillar are simulated to investigate the optimal water volume for double-self-assembly process. High alignment accuracy of misalignment measurement can be accomplished with the optimal water volume. Furthermore, microstructure of Cu/In bonded structures and corresponding electrical analyses are evaluated, while various reliability tests are investigated for bonding quality. Excellent results verify that the double-self-assembly technology could be applied to 3-D heterogeneous integration for uneven-topography-chip integration.

Original languageEnglish
Article number8194937
Pages (from-to)310-316
Number of pages7
JournalIEEE Transactions on Components, Packaging and Manufacturing Technology
Issue number2
StatePublished - 1 Feb 2018


  • 3-D heterogeneous integration
  • double-self-assembly technology

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