ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures

Po Hao Wang, Yung Chen Chien, Shang Jen Tsai, Xuan Yu Lin, Rizal Tanjung, Yi Sian Lin, Shu Wei Syu, Tay Jyi Lin, Jinn Shyan Wang, Tien-Fu Chen

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

An asymmetric architecture is commonly used in modern embedded systems to reduce energy consumption. The systems tend to execute more applications in the energy-efficient core, which typically employs ultralow voltage (ULV) to save energy. However, caches become a reliability and performance barrier that limits the minimum operating voltage and blocks system performance in the ULV environment. The poor performance of an ultralow-voltage core causes most workload requirements to awaken and then execute on the host core, leading to high energy consumption. In this paper, we propose a ULV-Turbo cache based on a ULV-selective-ally 8T static random access memory (SRAM) that is able to perform reliable ultralow-voltage operation and provide the speedup function of SRAM rows ally. The system is able to speed up the ULV core instantaneously and execute more applications with the ULV-Turbo cache. In our system-wide evaluation based on a real attitude and heading reference system workload on an asymmetric wearable system, the ULV-Turbo cache reduces the energy consumption of the entire system by approximately 36%.

Original languageEnglish
Article number7812737
Pages (from-to)3341-3354
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number12
DOIs
StatePublished - 1 Dec 2017

Keywords

  • Cache memory
  • low voltage
  • reliability
  • system energy saving
  • timing discrepancy reducing

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