Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

Yang Kyu Choi; Kazuya Asano; Nick Lindert; Vivek Subramanian; Tsu Jae King; Jeffrey Bokor; Chen-Ming Hu

doi:10.1109/55.841313

Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

Yang Kyu Choi, Kazuya Asano, Nick Lindert, Vivek Subramanian, Tsu Jae King, Jeffrey Bokor, Chen-Ming Hu

International College of Semiconductor Technology

Research output: Contribution to journal › Article › peer-review

174 Scopus citations

Abstract

A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance.

Original language	English
Pages (from-to)	254-255
Number of pages	2
Journal	IEEE Electron Device Letters
Volume	21
Issue number	5
DOIs	https://doi.org/10.1109/55.841313
State	Published - 1 May 2000

Access to Document

10.1109/55.841313

Fingerprint Dive into the research topics of 'Ultrathin-body SOI MOSFET for deep-sub-tenth micron era'. Together they form a unique fingerprint.

Cite this

@article{60d4babaf1c04937bbd307b27f1f89d0,

title = "Ultrathin-body SOI MOSFET for deep-sub-tenth micron era",

abstract = "A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance.",

author = "Choi, {Yang Kyu} and Kazuya Asano and Nick Lindert and Vivek Subramanian and King, {Tsu Jae} and Jeffrey Bokor and Chen-Ming Hu",

year = "2000",

month = may,

day = "1",

doi = "10.1109/55.841313",

language = "English",

volume = "21",

pages = "254--255",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

AU - Choi, Yang Kyu

AU - Asano, Kazuya

AU - Lindert, Nick

AU - Subramanian, Vivek

AU - King, Tsu Jae

AU - Bokor, Jeffrey

AU - Hu, Chen-Ming

PY - 2000/5/1

Y1 - 2000/5/1

N2 - A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance.

AB - A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance.

UR - http://www.scopus.com/inward/record.url?scp=0033750493&partnerID=8YFLogxK

U2 - 10.1109/55.841313

DO - 10.1109/55.841313

M3 - Article

AN - SCOPUS:0033750493

VL - 21

SP - 254

EP - 255

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 5

ER -

Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

Abstract

Access to Document

Other files and links

Cite this