Ultra-thin gate oxides - performance and reliability

Hiroshi Iwai*, Hisayo Sasaki Momose

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

60 Scopus citations

Abstract

Gate oxide thinning accompanied by the CMOS downsizing is expected to reach a direct-tunneling leakage current regime at the generations of 0.1 μm and below. This has been regarded as one of the limiting factor of CMOS progress in terms of performance. Recently, the studies of the direct-tunneling gate oxide have been carried out popularly and aggressively. In this paper, the results of these studies are reviewed and future prospects for the gate oxides are predicted.

Original languageEnglish
Pages (from-to)163-166
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 6 Dec 1998
EventProceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 6 Dec 19989 Dec 1998

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