Ultra-shallow junction formation using implantation through capping nitride layer on source/drain extension

Li Jen Hsien*, Yi Lin Chan, Tien-Sheng Chao, Yeu Long Jiang, Chung Yuan Kung

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

Method for forming ultra-shallow p+/n is demonstrated for 0.15 μm p-type metal-oxide-semiconductor field-effect transistor (pMOSFET). The approach includes a capping ultra-thin nitride on the source/drain extension regions followed by a low energy source/drain (S/D) extension implantation. Ultra shallow p+/n junctions can be obtained with depth of 27 nm and sheet resistivity of 1007 Ω/□.

Original languageEnglish
Pages (from-to)4519-4520
Number of pages2
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume41
Issue number7 A
DOIs
StatePublished - 1 Jul 2002

Keywords

  • CMOS
  • Nitride
  • Shallow junction

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