Ultra-low power green electronic devices

S. H. Yi, Albert Chin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Power consumption is the crucial challenge for electronics. To lower the DC leakage power (PDC), we applied the high-κ gate dielectric to CMOS from the physics of Q equivalent to CV. More than 2 orders of magnitude lower PDC is obtained at small 0.5-0.9 nm equivalent-oxide-thickness (EOT). The high-κ dielectric also increases the charge controllability of flash memory and decrease the VT disturbance by nearly cells, which improves cell density and cost. The AC power (PAC) can be lowered by using high-mobility Ge CMOS at a lower VD and 3D IC with a small capacitance, from basic physics of PAC equivalent to CVD2f/2.

Original languageEnglish
Title of host publicationProceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages285-288
Number of pages4
ISBN (Electronic)9781479983636
DOIs
StatePublished - 30 Sep 2015
Event11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore
Duration: 1 Jun 20154 Jun 2015

Publication series

NameProceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015

Conference

Conference11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
CountrySingapore
CitySingapore
Period1/06/154/06/15

Keywords

  • CMOS
  • Ge
  • flash memory
  • high-κ
  • ultra-low power

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