Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Po Yen Chiu*, Ming-Dou Ker, Fu Yi Tsai, Yeong Jar Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25°C, which is much smaller than that (613μA) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.

Original languageEnglish
Title of host publication2009 IEEE International Reliability Physics Symposium, IRPS 2009
Pages750-753
Number of pages4
DOIs
StatePublished - 12 Nov 2009
Event2009 IEEE International Reliability Physics Symposium, IRPS 2009 - Montreal, QC, Canada
Duration: 26 Apr 200930 Apr 2009

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Conference

Conference2009 IEEE International Reliability Physics Symposium, IRPS 2009
CountryCanada
CityMontreal, QC
Period26/04/0930/04/09

Keywords

  • Electrostatic discharge (ESD)
  • ESD clamp circuit
  • Gate leakage
  • Silicon-controlled rectifier (SCR)

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