Ultra-low leakage 0.16 μm CMOS for low-standby power applications

C. C. Wu*, C. H. Diaz, B. L. Lin, S. Z. Chang, C. C. Wang, J. J. Liaw, C. H. Wang, K. K. Young, K. H. Lee, B. K. Liew, J. Y.C. Sun

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

9 Scopus citations


In this work, low leakage 0.16um CMOS devices (Tox = 32 angstrom) with various off-state leakage currents (Ioff) were fabricated and studied for low standby power applications. Specifically two different device designs are introduced here. One design code named LP is targeted for worst-case Ioff < 3 pA/μm. Another design, code named ULP (ultra low-power), is targeted for even stringent worst-case Ioff < 0.3 pA/μm. This work demonstrates n/pMOSFETs with 575/230 and 370/165 μA/μm drive currents 1.8V for LP and ULP specifications respectively. Cobalt salicide process was also optimized for low junction leakage (< 100 pA/cm). The 0.16 μm process capability for ultra-low power applications was demonstrated using a CMOS 4Mbit SRAM with measured minimum standby current < 0.2 μA at the single power supply voltage Vcc = 3 V.

Original languageEnglish
Pages (from-to)671-674
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - 1999
Event1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA
Duration: 5 Dec 19998 Dec 1999

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