Two systolic architectures for multiplication in GF(2m)

W. C. Tsai*, Sheng-Jyh Wang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

21 Scopus citations


Two new systolic architectures are presented for multiplications in the finite field GF(2m). These two architectures are based on the standard basis representation. In Architecture-I, the authors attempt to speed up the operation by using a new partitioning scheme for the basic cell in a straightforward systolic architecture to shorten the clock cycle period. In Architecture-II, they eliminate the one clock cycle gap between iterations by pairing off the cells of Architecture-I. They compare their architectures with previously proposed systolic architectures and a semi-systolic architecture, and show that their Architecture-I offers the highest speed and Architecture-II the lowest hardware complexity.

Original languageEnglish
Pages (from-to)375-382
Number of pages8
JournalIEE Proceedings: Computers and Digital Techniques
Issue number6
StatePublished - 1 Nov 2000

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