TY - GEN
T1 - Two-staged parallel layer-aware partitioning for 3D designs
AU - Chen, Yi Hang
AU - Chen, Yi Ting
AU - Huang, Juinn-Dar
PY - 2014/1/1
Y1 - 2014/1/1
N2 - As compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a promising solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, minimizing the number of TSVs becomes an important design issue. Therefore, in this paper, we propose a parallel layer-aware partitioning algorithm, featuring both divergence stage and convergence stage, for TSV minimization in 3D structures. In the divergence stage, we employ OpenMP for the parallelization of 2-way min-cut partitioning and get the initial solution, and then refine it in the convergence stage. Experimental results show that the proposed two-staged algorithm can reduce the number of TSVs by up to 39% as compared to several existing methods.
AB - As compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a promising solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, minimizing the number of TSVs becomes an important design issue. Therefore, in this paper, we propose a parallel layer-aware partitioning algorithm, featuring both divergence stage and convergence stage, for TSV minimization in 3D structures. In the divergence stage, we employ OpenMP for the parallelization of 2-way min-cut partitioning and get the initial solution, and then refine it in the convergence stage. Experimental results show that the proposed two-staged algorithm can reduce the number of TSVs by up to 39% as compared to several existing methods.
UR - http://www.scopus.com/inward/record.url?scp=84904013053&partnerID=8YFLogxK
U2 - 10.1109/VLSI-DAT.2014.6834861
DO - 10.1109/VLSI-DAT.2014.6834861
M3 - Conference contribution
AN - SCOPUS:84904013053
SN - 9781479927760
T3 - Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
BT - Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
PB - IEEE Computer Society
Y2 - 28 April 2014 through 30 April 2014
ER -