Two-staged parallel layer-aware partitioning for 3D designs

Yi Hang Chen, Yi Ting Chen, Juinn-Dar Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a promising solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, minimizing the number of TSVs becomes an important design issue. Therefore, in this paper, we propose a parallel layer-aware partitioning algorithm, featuring both divergence stage and convergence stage, for TSV minimization in 3D structures. In the divergence stage, we employ OpenMP for the parallelization of 2-way min-cut partitioning and get the initial solution, and then refine it in the convergence stage. Experimental results show that the proposed two-staged algorithm can reduce the number of TSVs by up to 39% as compared to several existing methods.

Original languageEnglish
Title of host publicationTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
PublisherIEEE Computer Society
ISBN (Print)9781479927760
DOIs
StatePublished - 1 Jan 2014
Event2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan
Duration: 28 Apr 201430 Apr 2014

Publication series

NameTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Conference

Conference2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
CountryTaiwan
CityHsinchu
Period28/04/1430/04/14

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  • Cite this

    Chen, Y. H., Chen, Y. T., & Huang, J-D. (2014). Two-staged parallel layer-aware partitioning for 3D designs. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 [6834861] (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). IEEE Computer Society. https://doi.org/10.1109/VLSI-DAT.2014.6834861