Two-level hierarchical Z-buffer with compression technique for 3D graphics hardware

Cheng Hsien Chen*, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

The hierarchical Z-buffer is application-invisible and more efficient than the traditional Z-buffer for quickly rejecting hidden geometries. But there are construction and management issues associated with integrating a hierarchical Z-buffer into current graphics hardware. Here we present a two-level hierarchical Z-buffer algorithm, and provide solutions to these issues. Simulation results show that the bandwidth can be reduced by up to 35%. Moreover we propose a dynamic bi-level HZ-buffer compression technique that reduces the buffer size up by to 40%, and for which there is little performance degradation.

Original languageEnglish
Pages (from-to)467-479
Number of pages13
JournalVisual Computer
Volume19
Issue number7-8
DOIs
StatePublished - 1 Jan 2003

Keywords

  • 3D graphics hardware
  • Hierarchical Z-buffer
  • Hierarchical Z-buffer compression

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