Two experimental methods to characterize load capacitance of a CMOS gate

Kai Chen*, Chen-Ming Hu, Peng Fang, Min Ren Lin, Donald L. Wollesen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

The load capacitance of a CMOS gate has been experimentally characterized by two independent methods on the particular wafers fabricated for this study Agreement between the two methods is obtained and confirmed using CMOS ring oscillators with gate oxide thicknesses from 2.5 to 5.8 nm and effective channel lengths down to 0.21 μm at voltages from 1.5 to 3.3 V. This study provides the capacitance data for an analytical gate delay model.

Original languageEnglish
Pages (from-to)773-775
Number of pages3
JournalSemiconductor Science and Technology
Volume13
Issue number7
DOIs
StatePublished - 1 Jul 1998

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