Tunneling through multi-layer gate dielectrics - An analytical model

I. Polishchuk, Yee Chia Yeo, Tsu Jae King, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

We propose an analytical direct-tunneling model for multilayer gate dielectrics. This model predicts the amount of gate leakage current as a function of equivalent oxide thickness of the gate dielectric stack and the composition of the stack. This simple model is a useful tool in the development of future CMOS gate dielectric stacks.

Original languageEnglish
Title of host publication60th Device Research Conference, DRC 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages105-106
Number of pages2
ISBN (Electronic)0780373170
DOIs
StatePublished - 1 Jan 2002
Event60th Device Research Conference, DRC 2002 - Santa Barbara, United States
Duration: 24 Jun 200226 Jun 2002

Publication series

NameDevice Research Conference - Conference Digest, DRC
Volume2002-January
ISSN (Print)1548-3770

Conference

Conference60th Device Research Conference, DRC 2002
CountryUnited States
CitySanta Barbara
Period24/06/0226/06/02

Keywords

  • Analytical models
  • CMOS integrated circuits
  • Dielectrics
  • Electrons
  • Frequency
  • Leakage current
  • Predictive models
  • Semiconductor device modeling
  • Tunneling
  • Voltage

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