Tunnel FET-based pass-transistor logic for ultra-low-power applications

Sung Hwan Kim, Zachery A. Jacobson, Pratik Patel, Chen-Ming Hu, Tsu Jae King Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Germanium-source tunnel-FET-based pass-transistor logic gates are proposed and benchmarked against conventional CMOS logic gates via mixed-mode simulations, for 15 nm LG. For low throughput applications (>100 ps gate delay), TPTL is advantageous for reductions in dynamic energy and leakage power.

Original languageEnglish
Title of host publication69th Device Research Conference, DRC 2011 - Conference Digest
Pages133-134
Number of pages2
DOIs
StatePublished - 1 Dec 2011
Event69th Device Research Conference, DRC 2011 - Santa Barbara, CA, United States
Duration: 20 Jun 201122 Jun 2011

Publication series

NameDevice Research Conference - Conference Digest, DRC
ISSN (Print)1548-3770

Conference

Conference69th Device Research Conference, DRC 2011
CountryUnited States
CitySanta Barbara, CA
Period20/06/1122/06/11

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    Kim, S. H., Jacobson, Z. A., Patel, P., Hu, C-M., & Liu, T. J. K. (2011). Tunnel FET-based pass-transistor logic for ultra-low-power applications. In 69th Device Research Conference, DRC 2011 - Conference Digest (pp. 133-134). [5994452] (Device Research Conference - Conference Digest, DRC). https://doi.org/10.1109/DRC.2011.5994452