True 50% duty-cycle high-speed divider with the modulus of odd numbers

Sheng Che Tseng*, Hung Ju Wei, Jin Siang Syu, Chin-Chun Meng, Kuan Chang Tsung, Guo Wei Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper proposes a true 50% duty-cycle highspeed prescaler with an odd modulus, based on current switchable D flip-flops. Each D flip-flop can sample data at the positive and negative clock edges, because of the changeable trigger mode. The proposed divide-by-N prescaler, with a 50% duty cycle, is formed as a ring with an N number of D flip-flops. Two types of 50% duty-cycle divide-by-five prescalers, the sample-hold-sample-hold-hold (SHSHH) prescaler and the sample-sample-hold-sample-hold (SSHSH) prescaler, are implemented using the 0.35 μm SiGe HBT technology. The SHSHH divider has a better performance, up to 7 GHz, thanks to the synchronization of data and control signals.

Original languageEnglish
Title of host publicationAPMC 2009 - Asia Pacific Microwave Conference 2009
Pages305-308
Number of pages4
DOIs
StatePublished - 1 Dec 2009
EventAsia Pacific Microwave Conference 2009, APMC 2009 - Singapore, Singapore
Duration: 7 Dec 200910 Dec 2009

Publication series

NameAPMC 2009 - Asia Pacific Microwave Conference 2009

Conference

ConferenceAsia Pacific Microwave Conference 2009, APMC 2009
CountrySingapore
CitySingapore
Period7/12/0910/12/09

Keywords

  • 50% duty cycle
  • Divide-by-N
  • Prescaler
  • SiGe HBT

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