Trend of CMOS downsizing and its reliability

H. Iwai*, S. Ohmi

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

9 Scopus citations

Abstract

In this paper, CMOS downsizing trend into sub-70 nm node and further below is described. Downscaling of advanced CMOS devices have been significantly accelerated every time by the update of the ITRS roadmap. Now, on one hand, we can expect the realization of even sub-10 nm CMOS devices, but on the other hand, so many difficulties in technology for the downsizing are anticipated. In this paper, the difficulties and possible solutions are explained.

Original languageEnglish
Pages (from-to)1251-1258
Number of pages8
JournalMicroelectronics Reliability
Volume42
Issue number9-11
DOIs
StatePublished - 2002

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