TY - JOUR
T1 - Trend of CMOS downsizing and its reliability
AU - Iwai, H.
AU - Ohmi, S.
PY - 2002
Y1 - 2002
N2 - In this paper, CMOS downsizing trend into sub-70 nm node and further below is described. Downscaling of advanced CMOS devices have been significantly accelerated every time by the update of the ITRS roadmap. Now, on one hand, we can expect the realization of even sub-10 nm CMOS devices, but on the other hand, so many difficulties in technology for the downsizing are anticipated. In this paper, the difficulties and possible solutions are explained.
AB - In this paper, CMOS downsizing trend into sub-70 nm node and further below is described. Downscaling of advanced CMOS devices have been significantly accelerated every time by the update of the ITRS roadmap. Now, on one hand, we can expect the realization of even sub-10 nm CMOS devices, but on the other hand, so many difficulties in technology for the downsizing are anticipated. In this paper, the difficulties and possible solutions are explained.
UR - http://www.scopus.com/inward/record.url?scp=66049120838&partnerID=8YFLogxK
U2 - 10.1016/s0026-2714(02)00131-2
DO - 10.1016/s0026-2714(02)00131-2
M3 - Article
AN - SCOPUS:66049120838
VL - 42
SP - 1251
EP - 1258
JO - Microelectronics and Reliability
JF - Microelectronics and Reliability
SN - 0026-2714
IS - 9-11
ER -