Trapping properties of very thin nitride/oxide gate insulators

J. Y.C. Sun*, M. Arienzo, L. Dori, K. Stein

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The trapping properties of very thin nitride/oxide (10-14nm equivalent SiO2) composite gate insulators and their dependences on gate materials and process conditions are reported. Electron trapping and flatband voltage turn-around effects are more pronounced in these films than in thermal SiO2. They both appear to be dominated by water-related species in the bottom oxide layer when the top nitride layer is thin, similar to the case of thermal SiO2only. For VLSI CMOS applications, trapping and instabilities in the nitride/oxide gate insulator can be minimized by (i) reducing the thickness of the top nitride layer, (ii) using polysilicon gates with proper work functions, and (iii) using appropriate high-temperature dehydration steps after polysilicon gate deposition.

Original languageEnglish
Title of host publicationESSDERC 1987 - 17th European Solid State Device Research Conference
PublisherIEEE Computer Society
Pages841-844
Number of pages4
ISBN (Electronic)0444704779
ISBN (Print)9780444704771
StatePublished - 1987
Event17th European Solid State Device Research Conference, ESSDERC 1987 - Bologna, Italy
Duration: 14 Sep 198717 Sep 1987

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Conference

Conference17th European Solid State Device Research Conference, ESSDERC 1987
CountryItaly
CityBologna
Period14/09/8717/09/87

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    Sun, J. Y. C., Arienzo, M., Dori, L., & Stein, K. (1987). Trapping properties of very thin nitride/oxide gate insulators. In ESSDERC 1987 - 17th European Solid State Device Research Conference (pp. 841-844). [5436773] (European Solid-State Device Research Conference). IEEE Computer Society.