Transient-induced latchup in CMOS integrated circuits due to Electrical Fast Transient (EFT) test

Cheng Cheng Yen*, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

The transient-induced latchup (TLU) in CMOS ICs under electrical fast transient (EFT) test has been investigated by experimental verification. With positive and negative voltage pulses under EFT test, the TLU can be triggered on in CMOS ICs with the parasitic pnpn structure. The physical mechanism of TLU in CMOS ICs has been developed with experimental verification in time domain. All the experimental evaluations have been verified With the silicon-controlled rectifier (SCR) test structure fabricated in a 0.18-∝m CMOS technology.

Original languageEnglish
Title of host publicationProceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007
Pages253-256
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Bangalore, India
Duration: 11 Jul 200713 Jul 2007

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits
CountryIndia
CityBangalore
Period11/07/0713/07/07

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