Transient-induced latchup dependence on power-pin damping frequency and damping factor in CMOS integrated circuits

Sheng Fu Hsu*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

The bipolar (underdamped sinusoidal) transient noise on power pins of CMOS integrated circuits (ICs) can trigger latchup in CMOS ICs under system-level electrostatic-discharge test. Two dominant parameters of bipolar transient noise-damping frequency and damping factor-strongly depend on system shielding, board-level noise filter, chip-/board-level layout, etc. The transient-induced-latchup (TLU) dependence on power-pin damping frequency and damping factor was characterized by device simulation and verified by experimental measurement. From the simulation results, bipolar-trigger waveforms with damping frequencies of several tens of megahertz can trigger the TLU most easily. However, TLU is less sensitive to the bipolar-trigger waveforms with an excessively large damping factor or an excessively low/high damping frequency. The simulation results have been experimentally verified with the silicon-controlled-rectifier (SCR) test structures that are fabricated in a 0.25-μm CMOS technology.

Original languageEnglish
Pages (from-to)2002-2010
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume54
Issue number8
DOIs
StatePublished - 1 Aug 2007

Keywords

  • Bipolar-trigger voltage
  • Latchup
  • Silicon-controlled rectifier (SCR)
  • System-level electrostatic-discharge (ESD) test
  • Transient-induced latchup (TLU)

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