Transient device simulation of trap-assisted leakage in non-volatile memory cell

Hiroshi Watanabe*

*Corresponding author for this work

Research output: Contribution to conferencePaper

1 Scopus citations

Abstract

In order to study how a local trap degrades data retention characteristics of floating gate nonvolatile memory cell, a general-purpose Single-Electron Device Simulator (SEDS) developed for Si-dot is improved to carry out a very wide range transient analysis from 0.1 pico-seconds to 10 years. As a result, it is found that the data retention is degraded by the direct tunneling enhanced due to positive charge stored at the trap inside the inter-poly dielectric but not by trap-assisted tunneling.

Original languageEnglish
Pages45-48
Number of pages4
DOIs
StatePublished - 1 Dec 2008
Event2008 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2008 - Hakone, Japan
Duration: 9 Sep 200811 Sep 2008

Conference

Conference2008 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2008
CountryJapan
CityHakone
Period9/09/0811/09/08

Keywords

  • Device-simulation
  • Local trap
  • Nonvolatile memory
  • Transient analysis

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    Watanabe, H. (2008). Transient device simulation of trap-assisted leakage in non-volatile memory cell. 45-48. Paper presented at 2008 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2008, Hakone, Japan. https://doi.org/10.1109/SISPAD.2008.4648233