Toward 44% switching energy reduction for FinFETs with vacuum gate spacer

Kehuey Wu*, Angada Sachid, Fu Liang Yang, Chen-Ming Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Up to 44% reduction in switching energy or 22% reduction in ring oscillator delay time are obtained in simulations by FinFET gate spacer optimization. Using vacuum spacer instead of nitride spacer required for future self-aligned contact technology, the fringing gate capacitance can be lowered by 15%, which results in significant speed increase and energy consumption reduction. The speed benefit can be leveraged to further lower the supply voltage and energy consumption. The vacuum spacer can provide relief to this trend.

Original languageEnglish
Title of host publicationInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2012 Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages253-256
Number of pages4
ISBN (Electronic)9780615717562
StatePublished - Sep 2012
Event2012 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2012 - Denver, United States
Duration: 5 Sep 20127 Sep 2012

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Conference

Conference2012 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2012
CountryUnited States
CityDenver
Period5/09/127/09/12

Keywords

  • Air Spacer
  • CMOS
  • FinFET
  • Multi-Gate
  • Spacer Optimization
  • Vacuum Spacer

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